Many FET read only memory circuits have been described in the prior art, wherein a binary one or a binary zero is selectively stored at a particular location at the time of fabrication of the circuit, by permanently altering the conductivity of the FET storage device. When large arrays of such read only memory devices are connected in parallel to a charging node, significant problems can arise due to the leakage of charge from the node during intervening quiescent periods between the precharge stage and the conditional discharge stage. If significant quantities of charge have bled away from a node which is to be sensed for its state to indicate whether a binary one or a binary zero was stored at the accessed location, then the result of that binary sensing can be ambiguous.